ASIC Engineer, Design Verification

Meta · India · Posted 17 days ago

About this role

As a Design Verification Engineer at Meta, you will be part of a dynamic team working with the best in the industry to develop innovative ASIC solutions for data center applications and wearables. You will be responsible for the verification closure of design modules or sub-systems from test-planning, UVM-based test bench development to verification closure. Along with traditional simulation, you will use other approaches like Formal and Emulation to achieve bug-free designs. ASIC Engineer, Design Verification Responsibilities: • Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification • Develop functional tests based on verification test plan • Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage • Debug, root-cause and resolve functional failures in the design, partnering with the Design team • Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality through defined verification metrics and coverage goals • Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry Minimum Qualifications: • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience • 8+ years of experience in SystemVerilog/UVM (Universal Verification Me